ALTERA verilog Error (12007):Top-level design entity is undefined

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ALTERA verilog Error(12007):Top-level design entity “led”is undefined
在新建工程的时候,代码首个模块需要和新建的名称对应.

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module led(
    input      key_in,
    output     led_out
);
assign led_out = ~key_in;
endmodule //led

设置如下: